AD9985A/PCBZ【PDF 19/32 页】KIT EVALUATION FOR AD9985A

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AD9985A

Write and

Hexadecimal

Read or

Default

Register

Address

0x16

Read-Only

R/W

Bits

7

Value

0*******

Name

Extra PLL

Function

Bit 7—Extra PLL Divider. (Logic 0 = off, Logic 1 = extra divide-by-2).

Divider

6:5

*00*****

SOGIN

Bandwidth

Bits [6:5]—SOGIN Bandwidth Control; 00 = 300 MHz;

01 or 10 = 13 MHz; 11 = 6.5 MHz.

Control

4

***0****

Analog Input

Bandwidth

Bit 4—Sets the bandwdith of the red, green and blue analog inputs.

(Logic 0 = 300 MHz, Logic 1 = 7 MHz).

Control

3:0

****0000

Reserved

Reserved.

0x17

0x18

RO

RO

7:0

7:0

Test Register

Test Register

Reserved.

Reserved.

0x19

R/W

7:0

00000100

Red Target

Target Code for Auto-Offset Operation.

Code

0x1A

R/W

7:0

00000100

Green Target

Target Code for Auto-Offset Operation.

Code

0x1B

R/W

7:0

00000100

Blue Target

Target Code for Auto-Offset Operation.

Code

0x1C

0x1D

R/W

R/W

7:0

7

00010001

0*******

Reserved

Auto Offset

Must be written to 0x11 for proper operation.

Enables the auto-offset circuitry.

Enable

6

*0******

Hold Auto

Holds the offset output of the auto-offset at the current value.

Offset

5:2

1:0

**1001**

******10

Reserved

Update Mode

Must be written to 9 for proper operation.

Changes the update rate of the auto-offset.

0x1E

R/W

7:0

0000****

Test Register

Must be set to default value.

1

The AD9985A only updates the PLL divide ratio when the LSBs are written to (Register 0x02).

2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP

IDENTIFICATION

VESA has established some standard timing

specifications that assist in determining the value for

00

7–0 Chip Revision

An 8-bit register that represents the silicon revision.

PLLDIV as a function of horizontal and vertical

display resolution and frame rate (Table 8).

PLL DIVIDER CONTROL

However, many computer systems do not conform

precisely to the recommendations, and these numbers

01

7–0 PLL Divide Ratio MSBs

The 8 most significant bits of the 12-bit PLL divide

ratio PLLDIV. (The operational divide ratio is

PLLDIV + 1.)

The PLL derives a master clock from an incoming

Hsync signal. The master clock frequency is then

divided by an integer value, such that the output is

phase-locked to Hsync. This PLLDIV value

determines the number of pixel times (pixels plus

horizontal blanking overhead) per line. This is

typically 20% to 30% more than the number of active

pixels in the display.

should be used only as a guide. The display system

manufacturer should provide automatic or manual

means for optimizing PLLDIV. An incorrectly set

PLLDIV usually produces one or more vertical noise

bars on the display. The greater the error, the greater

the number of bars produced.

The power-up default value of PLLDIV is 1693

(PLLDIVM = 0x69, PLLDIVL = 0xDx).

The AD9985A updates the full-divide ratio only when

the LSBs are changed. Writing to the MSB by itself

does not trigger an update.

The 12-bit value of the PLL divider supports divide

ratios from 2 to 4095. The higher the value loaded in

this register, the higher the resulting clock frequency

with respect to a fixed Hsync frequency.

02

7–4 PLL Divide Ratio LSBs

The 4 least significant bits of the 12-bit PLL divide

ratio PLLDIV. The operational divide ratio is

PLLDIV + 1.

Rev. 0 | Page 19 of 32

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